The present invention relates generally to semiconductor devices, and particularly to static induction transistors (SIT).
Conventional SITs are initially discussed herein for a better understanding of the present invention. FIG. 1 is a cross-sectional view of structure of a conventional juntion gate type SIT, which is formed vertically (i.e., in a direction of the thickness of a substrate). This SIT comprises an n.sup.+ type source region 101, an n.sup.+ type drain region 102, a p.sup.+ type gate region 103 and an epitaxial region 104, used as a channel portion. The SIT has a channel with a small size compared to that of a field effect transistor (FET), and a low impurity concentration (approximately from 10.sup.12 to 10.sup.15 cm.sup.-3). Thereby, in response to the gate being biased to zero or a slight reverse voltage being applied to gate, the SIT is energized to a pinch-off state in which the channel is completely covered by the depletion layer. Under these circumstances a saddle point potential barrier 201 appears in front of the source as shown in FIG. 2. The height of the potential barrier controls the flow rate of carriers mainly flowing from the source to drain (this potential barrier having an intrinsic gating function). Carriers flowing from the source to drain over the saddle point potential barrier, which is also referred to as intrinsic gate barrier, concentrate on the channel center region 202.
FIG. 3 is an X-Y-Z plot of potential distribution in a prior art SIT. Potential distributions A' and B' are respectively viewed along dotted lines A and B in FIG. 1. The center of the source is located at (0, 0), and the distance along the Y axis indicates distance from the source toward the drain. The gate is located along the Y axis at Y=Y.sub.G, and the gate voltage is indicated at X=.+-.X.sub.G. The drain is located at Y=Y.sub.D, while the source is located at Y=0. The depletion layer extends from Y.sub.G toward the source to Ys and toward the drain to Yd. The height, .PSI.o, of the intrinsic gate barrier decreases in proportion to the drain voltage while the position of the barrier is shifted toward the source. Therefore the number of carriers climbing over the barrier increases so that unsaturated current-voltage (I-V) characteristics inherent to SIT are exhibited.
This unsaturated characteristic occurs because the height of the barrier of the intrinsic gate depends on both the gate voltage and the drain voltage. The unsaturated characteristic makes it difficult to obtain sufficient voltage gain. More specifically, assume that gain of a single stage amplifier is given by: ##EQU1## wherein g.sub.m =(.differential.I.sub.D /.differential.V.sub.G): transconductance;
r.sub.D =1/(.differential.I.sub.D /.differential.V.sub.G): drain internal resistance; PA1 R.sub.L : load resistance; PA1 I.sub.D : drain current; PA1 V.sub.G : gate voltage; PA1 V.sub.D : drain voltage. PA1 .beta.: a device constant. PA1 .beta.': a device constant. PA1 Q(t): amount of untransferred charges; PA1 Q.sub.0 : total amount of charge before transfer. PA1 g.sub.r : reverse transmission conductance; PA1 .epsilon..sub.SS : transfer loss due to surface level; PA1 C.sub.BS : effective interface (or surface) state capacitance of MOSFET Q.sub.2 ; PA1 V.sub.BO : potential of C.sub.B when no charge to be transferred to C.sub.D is in C.sub.B ; PA1 V.sub.BSC : potential of C.sub.BS when no charge transferrable to C.sub.D is in C.sub.BS ; PA1 V.sub.B : potential of C.sub.B ; PA1 V.sub.BS : potential of C.sub.BS. PA1 .epsilon..sub.i : transfer loss determined by the intrinsic transfer limit; PA1 .epsilon..sub.D : transfer loss determined by feedback effect (Dynamic Drain Conductance, referred to as DDC hereinafter) from capacitance C.sub.D to capacitance C.sub.B ; PA1 .epsilon..sub.C : transfer loss determined by modulation of storing capacitance C.sub.B by signal charges; PA1 .epsilon..sub.C, SS : transfer loss due to modulation of interface (or surface) state capacitance C.sub.BS by the signal charges; PA1 .epsilon..sub.i, SS : transfer loss due to intrinsic transfer limitation through interface (or surface) state. PA1 Cch: sum of gate oxide film capacitance and capacitance between channel and substrate. PA1 L: channel length; PA1 .mu.: mobility; PA1 C.sub.G : gate capacitance at transfer channel; PA1 V.sub.B *: potential at channel entrance. PA1 V.sub.S *: potential at channel entrance, having a relationship similar to Eq. (17) with V.sub.S ; PA1 L.sub.G1 : channel length; PA1 C.sub.G1 : gate capacitance.
From the above equation, voltage gain is optimized when the value of r.sub.D is relatively large, so it has saturated characteristics.
When the saturated charcteristics are achieved by a negative feedback effect due to the presence of a source internal resistance r.sub.s, in the same manner as generally provided in FETs, the apparent transconductance g.sub.m, is given by the following equation: ##EQU2##
Generally in the past the apparent transconductance g'.sub.m has been mistaken as the inherent transconductance of an FET. As r.sub.s becomes larger, g.sub.m ' becomes smaller than g.sub.m.
However, up to the present time, there has been no principle proposed for providing saturated characteristics without increasing r.sub.s with the large g.sub.m obtained by an unsaturated SIT. For practical applications, active devices having a potential setting function (based on saturated characteristics), as often used in integrated circuits, cannot be provided by an SIT structure.
One approach for providing high-speed active element operation is to use a tunnel transistor generally having an unsaturated V-I characteristic. This unsaturated characteristic occurs because the tunneling probability at the tunnel barrier depends on the voltages at the gate and drain regions; it has the disadvantage of the same small voltage gain shown by Eq. (1). Up to the present time, no consideration has been made of tunnel transistors having saturated characteristics.
In semiconductor memories and solid state imaging devices or the like, potential setting for vertical transmission lines or the like is necessary for transferring charge from a vertical transmission line forming a large capacitance charge storing region to a small capacitance charge storing region; a typical device of this type is known as a charge priming device (CPD).
FIG. 4A is a cross-sectional view of a basic CPD; FIG. 4B is an equivalent circuit of the CPD of FIG. 4A; and FIG. 4C is a timing diagram of driving pulses for the CPD. In FIG. 4A, capacitance C.sub.S is a charge-storing portion of an n.sup.+ region 401 formed on a p substrate 404, and capacitances C.sub.B and C.sub.D are respectively charge-storing portions of n.sup.+ regions 402 and 403. The capacitance values usually have the relationship C.sub.S &gt;C.sub.B &gt;C.sub.D as a general condition for using the CPD.
Inverted layer 405 between n.sup.+ regions 401 and 402 is formed when a voltage is applied to electrode TG1, to turn on MOSFET Q1. Similarly, when MOSFET Q2 turns on in response to a voltage being applied to electrode TG2, an inverted layer 406 is formed between n.sup.+ regions 402 and 403.
Initial potential setting is provided by setting the voltage at the n.sup.+ region 403 to V.sub.0 by closing switch 408. After this switch 408 is opened, Resistor R.sub.L detects a signal.
The potential of the n.sup.+ region 402 is set to a channel voltage V.sub.1 of an inverted layer 406, formed when the MOSFET Q2 turns on in response to the application of a voltage at the transfer gate electrode TG2. The voltage V.sub.1 is determined by the voltage applied to the transfer gate electrode TG2, and is normally in a state of V.sub.1 &lt;V.sub.0.
Similarly, the potential of the n.sup.+ region 401 is set to a channel voltage V.sub.2 of an inverted layer 405 formed when the MOSFET Q1 turns on in response to the application of a voltage at the transfer gate electrode TG1. The voltage V.sub.2 is determined by the voltage applied to the transfer gate electrode TG1; normally V.sub.2 &lt;V.sub.1.
Charge transfer is carried out by priming transfer means from the n.sup.+ region 401 to the n.sup.+ region 403, as described infra. The above-mentioned priming transfer is described with reference to the timing chart of FIG. 4C.
When t=t.sub.1, a high level of drive pulse .phi..sub.TG1 is applied to the electrode TG1. At this time, the MOSFET Q1 turns on and an internal bias charge Q.sub.B =(V.sub.2 -V.sub.1).times.C.sub.B corresponding to the difference (V.sub.2 -V.sub.1) between the potential V.sub.1 at the n.sup.+ region 402 and the potential V.sub.2 at the inverted layer 405 is injected from the equivalent capacitance C.sub.B of the n.sup.+ region 402 to the equivalent capacitance C.sub.S of the n.sup.+ region 401. This phenomenon is referred to as fill-in. When capacitance C.sub.S has an initial charge Q.sub.S, the resultant charge on capacitor C.sub.S is Q.sub.S +Q.sub.B.
Subsequently, when t=t.sub.2, the pulse .phi..sub.TC is applied to the electrode TC while pulse .phi..sub.TG1 is maintained at the high level. Because a static induction effect occurs between electrode TC and n.sup.+ region 402 via capacitance C.sub.0 of insulator 407, a potential fluctuation .DELTA.V is superimposed on the potential V.sub.2 of the n.sup.+ region 402 so that the potential at the n.sup.+ region 402 is (V.sub.2 +.DELTA.V)=V.sub.3 (&gt;V.sub.2).
As a result, charge (Q.sub.S +Q.sub.B) is transferred from the n.sup.+ region 401 (at the voltage V.sub.2) to the n.sup.+ region 402 (having an equivalent capacitance C.sub.B) at a further deep potential V.sub.3. This phenomenon is referred to as spill-out.
The combination of the above-mentioned fill-in and spill-out is referred to as fill-spill transfer, and transfer loss E.sub.P is given by the following equation when there is only an intrinsic tranfer limitation (see "DENSHI-ZAIRYO" Vol. 19, No. 12, 1980, Yamada et al): ##EQU3## where t.sub.TG1 : high level period of .phi..sub.TG1 ;
When Q.sub.S =0, Eq. (3) can be simplified as: ##EQU4##
At t=t.sub.3, the pulses .phi..sub.TG1 and .phi..sub.TC respectively have low and high levels. With this operation, the MOSFET Q1 is turned off, and the charge (Q.sub.S +Q.sub.B) is transferred to the n.sup.+ region 402 (equivalent capacitance Q.sub.B). With the above operations, fill-spill transfer is completed.
Subsequently, at t=t.sub.4, the pulse .phi..sub.TC has a low level, and the potential at the n.sup.+ region 402 (equivalent capacitance Q.sub.B) returns to the initial potential V.sub.1. At this time, a portion of n.sup.+ region 402 having a potential lower than V.sub.1 stores charge Q.sub.S.
Finally, at t=t.sub.5, a high level of pulse .phi..sub.TG2 is applied to the electrode TG2, causing the channel 406 to assume a potential of V.sub.1. As a result, only the signal charge Q.sub.S, having a potential lower than V.sub.1, the n.sup.+ region 402 (equivalent capacitance Q.sub.B) is transferred to the n.sup.+ region 403 (equivalent capacitance C.sub.D). This is referred to as skimming transfer, with a transfer loss E.sub.S given by the following equation during only intrinsic transfer limitation: ##EQU5## where t.sub.TG2 : high level period of .phi..sub.TG2 ;
With the above operations, one charge priming transfer cycle, i.e., the combination of a fill-spill transfer and a skimming transfer, is completed.
During charge priming transfer (referred to as CPT hereinafter), charge Q.sub.S is transferred from large capacitance C.sub.S to small capacitance C.sub.D. This means that the potential at the n.sup.+ region 401 can be set from the n.sup.+ region 403.
It is necessary to consider how small the transfer loss of Eqs. (3) and (5) can be set to determine the operation of the CPT structure.
Prior to considering the transfer loss, let us partially differentiate Eq. (3) with respect to Q.sub.B : ##EQU6##
From Eq. (7), when Q.sub.B increases, E.sub.P decreases. This means that Q.sub.S is regarded as a portion of Q.sub.B so as to be equivalent to the variation of Q.sub.B ; therefore, there is a possibility that E.sub.P can be modulated by Q.sub.S.
Assuming that Q.sub.S =0, Eq. (7) is simplified as Eq. (8): ##EQU7##
From Eqs. (3)' and (8), when E.sub.P .ltoreq.1/10 (which can be readily achieved), .differential.E.sub.P /.differential.Q.sub.B nearly equals 0, and it will be understood that the effect of modulation of E.sub.P by Q.sub.S can be neglected.
Now consider Eq. (5). Since the skimming transfer loss E.sub.S shown by Eq. (5) depends on signal charge Q.sub.S, there is a significant problem of how much the loss E.sub.S can be reduced when the signal charge Q.sub.S is small.
While C.sub.S &gt;C.sub.B &gt;C.sub.D, assuming that C.sub.S =10.times.C.sub.B, .beta..perspectiveto..beta.', and t.sub.TG1 .perspectiveto.t.sub.TG2, then we obtain A.sub.S .perspectiveto.10.sup.2 A.sub.p. Assuming E.sub.P (Q.sub.S =0)=0.1 when Q.sub.B /q=10.sup.6, as can be most readily realized, E.sub.S .perspectiveto.0.1 when Q.sub.S /Q10.sup.4 ; this value is too large for a transfer loss. If fill-spill transfer occurs between capacitances C.sub.B and C.sub.D, in place of skimming transfer to reduce the transfer loss, uniform setting would be difficult even though the number of bias charges Q.sub.B ' required is only between 10.sup.2 to 10.sup.3.
If C.sub.S =10.sup.2 .times.C.sub.B, A.sub.S .perspectiveto.10.sup.4 A.sub.P would occur with a similar argument; therefore, even if Q.sub.S /q=10.sup.2, E.sub.S .perspectiveto.0.1, providing no problem as to transfer loss with skimming transfer. However, the internal bias Q.sub.B necessary for fill-spill transfer cannot be stored in capacitance C.sub.B.
Let us consider Eq. (3)' which is a simplified form of Eq. (3). when considering E.sub.P =0.1 as a reference at Q.sub.B /q=10.sup.6 which can be readily provided when the value of Q.sub.B /q is as much as 4.times.10.sup.6, then E.sub.P =0.01, whereby there is no transfer loss problem in fill-spill transfer. However, it is difficult to find an optimal condition since the necessity of storing a large charge Q.sub.B in capacitance C.sub.B is contradictory to the necessity of reducing capacitance C.sub.B for skimming transfer loss reduction.
Consider a general incomplete transfer since fill-spill transfer in the CPD is an incomplete transfer with bias charges and skimming transfer is also an incomplete transfer without bias charges.
Generally speaking, the charge transfer occurring as FETs operate under a saturated condition is known as an incomplete transfer; transfer loss .epsilon.(t) in such an incomplete transfer is given by: EQU .epsilon.(t)=dQ(t)/dQ.sub.0 ( 9)
wherein
A differential equation relating to .epsilon. is as follows as related to charge Q.sub.2, FIG. 4: ##EQU8## wherein g.sub.m : forward transmission conductance;
A solution of Eq. (10) is: EQU .epsilon.=.epsilon..sub.i +.epsilon..sub.D +.epsilon..sub.C +.epsilon..sub.C,SS +.epsilon..sub.i,SS ( 11)
wherein
Results of each term of Eq. (11) are as follows: ##EQU9## wherein Q.sub.SS : total charges within interface (or surface) state;
Since .epsilon..sub.i,SS &lt;&lt;.epsilon..sub.C,SS, .epsilon..sub.i,SS is ignored hereinafter.
Among the above transfer losses, it can be readily proved that Eq. (12) is equivalent to Eq. (5).
Namely, when we use the following equations by a linear approximation using a rectangular transfer pulse, EQU g.sub.m .perspectiveto.dI/dV.sub.B, EQU dt.perspectiveto.(C.sub.B /I)dV.sub.B
then Eq. (12) is rewritten as: EQU .epsilon..sub.i .perspectiveto.I(t)/I.sub.0 =dQ(t)/dQ.sub.0
Therefore, the square law V-I characteristic of a MOSFET is exhibited. ##EQU10## wherein W: channel width;
Therefore, we obtain: ##EQU11##
Solving the above equation, we obtain Eq. (5).
To further expand Eqs. (12) through (16), it is necessary to consider g.sub.m and g.sub.r. Since V.sub.B is not generally equal to V.sub.B *, EQU dV.sub.B /dV.sub.B *=(1+kT/qV.sub.B *) (19)
Since: ##EQU12## wherein L.sub.G2 : channel length of MOSFET Q2,
Eq. (13) is rewritten as: ##EQU13##
Eqs. (14) and (15) represent transfer losses due to the charge capacitance modulation; since such transfer loss is equivalent to channel length modulation effect, these losses are expressed by: ##EQU14## wherein C.sub.G2 : gate capacitance. ##EQU15##
From Eqs. (13)' to (15)', the transfer losses .epsilon..sub.D, .epsilon..sub.C, .epsilon..sub.C'SS are determined by a feedback term: ##EQU16## known as a DDC effect.
Next, applying Eq. (9) to MOSFET Q.sub.1 of FIG. 4, transfer losses in connection with fill-spill transfer are obtained in the same manner as in the case of MOSFET Q.sub.2. This case differs from skimming transfer in that internal bias charges Q.sub.B exist; transfer losses due to the internal bias charges are given as follows in correspondence with Eqs. (12), (13)' to (15)' (portions corresponding to fill-spill transfer are indicated by): ##EQU17## where K indicates the effect of Q.sub.B as an equivalent and representing an improved effect of g.sub.m
From Eqs. (23) to (25), it will be understood that the transfer losses .epsilon..sub.D, .epsilon..sub.C, .epsilon..sub.C,.sub.SS are determined, even in the case of fill-spill transfer, by a feedback term: ##EQU18## which is known as DDC effect.
From Eqs. (20) and (21), we obtain: ##EQU19##
From the above, the DDC effect is determined by (g.sub.r /g.sub.m) and (g.sub.r /g.sub.m).
Therefore, it is also understood that transfer losses of any types are determined by (1/g.sub.m) and (1/g.sub.m) or by (g.sub.r /g.sub.m) and (g.sub.r /g.sub.m), where the contributions of g.sub.m and g.sub.m are great. Similarly, the contributions of g.sub.r and g.sub.r are great. This means that it is desired to increase g.sub.m and g.sub.m and reduce g.sub.r and g.sub.r to reduce the transfer losses to a negligible extent. This indicates that it is desired to have FETs with ideal saturation characteristics and large g.sub.m.
In addition, in solid state imaging devices, high-density is required for achieving miniaturization and providing high resolution, but such high-density is difficult to achieve because it causes a reduction in sensitivity. For this reason, solid state imaging devices having high multiplying sensitivity factors are desirable.
Conventional devices having high sensitivity multiplying factors are obtained by replacing photodiodes with phototransistors. Such phototransistors are formed as bipolar transistors (BPT) or field effect transistors (FET). In addition, a solid state imaging device using static induction transistors (SIT) having characteristics better than a BPT or a FET has been proposed in Japanese patent provisional publication Nos. 58-105672, 59-45781. When an SIT is used as a phototransistor, a device having a high sensitivity multiplying factor having inherent high g.sub.m (transconductance) can be obtained. However, since an SIT exhibits unsaturated V-I characteristics, similar to those of a vacuum tube triode, an undesirable feedback (dynamic drain conductance (DDC) effect occurs when the device is used for charge storing. Thereby, the gate potential barrier is modulated, which introduces a problem of the multiplying factor varying depending on the intensity of incident light.
Furthermore, it is difficult to have high sensitivity by sensitivity multiplication unless there is substantial removal of fixed pattern noise (FPN) occurring due to geometrical nonuniformity (such as photolithographic variations) and electrical nonuniformity (such as variations in threshold voltage or storage capacitances) of elements forming a light-receiving portion.
The above-described SITs are further described in the following documents:
(1) Nishizawa et al: IEEE Trans. Vol. ED-22, No. 4 (1975), "Field-Effect Transistor Versus Analog Transistor" (pages 185-197) which discusses the difference in operation between an FET and an SIT. PA0 (2) Mochida et al: IEEE Trans. Vo. ED-25, No. 7 (1978), "Characteristics of Static Induction Transistor" (pages 761-767) which shows clearly that an ideal limit of an FET is an SIT. PA0 (3) Ohmi et al: IEEE Trans. Vo. ED-27, No. 3 (1980), "Punching Through Device and Its Integration" (pages 536-545) which shows clearly the saddle point potential barrier characteristics inherent to an SIT.
However, the above-mentioned problems are left unsolved in these documents.